Graphics controller chips, like many integrated circuit devices, utilize CMOS, logic cores, and associated input/output (I/O) pads as part of their circuit makeup. I/O pads include, for example, input/output buffers coupled to a common pad or pin. There is a constant challenge to continuously design smaller, faster and more complicated integrated circuits to provide increased functionality for multimedia applications and other applications. Typically, the logic core operates at a different supply voltage than the I/O pads. For example, with logic cores having gate lengths of 0.25 um and gate oxide thickness' of 50 angstroms, a core logic supply voltage may be 2.5 volts. Corresponding supply voltages for the input/output pads, however, may be different supply voltages such as 3.3 volts. However, future generation chips require faster speeds and lower power consumption, hence, lower supply voltages so that the I/O pads can switch at faster frequencies.
Also, integrated circuits must often provide compatibility with older versions of interface circuits. As a result, an integrated circuit may require that the I/O pads operate at either a 3.3 volt level, or for example, at a lower 1.5 volt level. The gate length and gate thickness of I/O pad transistors must also typically be decreased to provide faster circuits that draw less current. With multilevel supply voltages, multi-gate oxide devices are often used to provide the requisite logic levels and overvoltage protection. However, a problem arises when multi-gate oxide transistors are used on the same chip. Using differing gate oxide thickness' requires additional fabrication processes and, hence, results in higher fabrication costs. Moreover, the larger gate oxide thickness can slow the device down unnecessarily. For low voltage CMOS signaling, the input/output pad must also be designed to prevent static leakage and prevent damage due to gate-source or gate-drain overvoltage.
Input/output interfaces that receive high speed CMOS signals, such as I/O pad receivers may send false signals because of signal reflections, power or ground noise and other sources of noise. A conventional input receiver circuit for such I/O interfaces uses a Schmidt Trigger receiver with hysteresis. One example is shown FIG. 1. As shown, a Schmidt Trigger receiver receives an input signal 12 which is coupled to a cascaded pair of pmos FET transistors 14 and cascaded nmos FET transistor 16. Feedback transistors 18 and 20 provide hysteresis so that ambient noise on the input signal is filtered. However, such Schmidt Trigger receivers are temperature sensitive and voltage supply fluctuates may pass through to the output. As such, noise on the voltage supply may not be suitably filtered.
It has been recommended to use differential input receivers with a voltage reference of a first stage of an input receiver to meet timing requirements of high speed input/output interfaces. For example, accelerated graphics port (AGP) design guides set forth by Intel Corporation (Revision 1.0, August, 1998) describes an input receiver having a differential input buffer with an external voltage reference. Such a differential input receiver is suggested to have a multi-stage input or folded cascade receiver configuration (AGP Design Guide Ref. 1.0, Section 1.4, pages 25-30.) Such a differential input receiver may have advantages over conventional single input Schmidt Trigger receivers since power supply noise may be reduced. However, noise on the input signal may not be suitably filter. Moreover, it is difficult to combine single input Schimdt Trigger input receiver and the differential input receiver.
Consequently, a need exists for an integrated circuit differential input receiver that can accommodate an external reference voltage as an input and an input signal as another input while providing suitable noise reduction.